A processor has one general purpose register, the Accumulator (ACC), and several special purpose registers.
(a) Complete the following description of the role of the registers in the fetch-execute cycle by writing the missing registers.
The ................................ holds the address of the next instruction to be loaded. This address is sent to the ................................ . The ................................ holds the data fetched from this address. This data is sent to the ................................ and the Control Unit decodes the instruction's opcode. The ................................ is incremented.
(b) The following table shows part of the instruction set for a processor. The processor has one general purpose register, the Accumulator (ACC), and an Index Register (IX).
| Instruction | Opcode | Operand | Explanation |
|---|---|---|---|
| LDM #n | Immediate addressing. Load the number n to ACC | ||
| LDD <address> | Direct addressing. Load the contents of the location at the given address to ACC | ||
| LDI <address> | Indirect addressing: The address to be used is at the given address. Load the contents of this second address to ACC | ||
| LDX <address> | Indexed addressing. Form the address from <address> + the contents of the Index Register. Copy the contents of this calculated address to ACC | ||
| LDR #n | Immediate addressing. Load the number n to IX | ||
| MOV <register> | Move the contents of the accumulator to the given register (IX) | ||
| STO <address> | Store contents of ACC at the given address | ||
| ADD <address> | Add the contents of the given address to the ACC | ||
| INC <register> | Add 1 to the contents of the register (ACC or IX) | ||
| CMP <address> | Compare the contents of ACC with the contents of <address> | ||
| JPE <address> | Following a compare instruction, jump to <address> if the compare was True | ||
| JPN <address> | Following a compare instruction, jump to <address> if the compare was False | ||
| JMP <address> | Jump to the given address | ||
| OUT | Output to the screen the character whose ASCII value is stored in ACC | ||
| END | Return control to the operating system | ||
| LSL #n | Bits in ACC are shifted logically n places to the left. Zeros are introduced on the right hand end | ||
| LSR #n | Bits in ACC are shifted logically n places to the right. Zeros are introduced on the left hand end |
<address> can be an absolute address or a symbolic address. # denotes a denary number, e.g. #123
The current contents of the main memory and selected values from the ASCII character set are shown.
| Main Memory | ASCII code table (selected codes only) | ||
|---|---|---|---|
| Address | Instruction | ASCII code | Character |
| 200 | LDD 365 | 65 | A |
| 201 | CMP 366 | 66 | B |
| 202 | JPE 209 | 67 | C |
| 203 | INC ACC | 68 | D |
| 204 | STO 365 | ||
| 205 | MOV IX | ||
| 206 | LDX 365 | ||
| 207 | OUT | ||
| 208 | JMP 200 | ||
| 209 | END | ||
| 365 | 1 | ||
| 366 | 3 | ||
| 367 | 65 | ||
| 368 | 66 | ||
| IX | 0 | ||
Complete the trace table for the program currently in main memory.
| Instruction address | ACC | Memory address | IX | Output | |||
|---|---|---|---|---|---|---|---|
| 365 | 366 | 367 | 368 | ||||
| 1 | 3 | 65 | 66 | 0 | |||
(c)(i) The Accumulator currently contains the binary number: 00110101
Write the contents of the Accumulator after the processor has executed the following instruction:
LSL #2
(c)(ii) The Accumulator currently contains the binary number: 00110101
Identify the mathematical operation that the following instruction will perform on the contents of the accumulator.
LSR #3